Processor systems, e.g., multi-processor systems, maintain different power states for the purpose of optimizing DC power savings. Processor systems may incorporate a DC power management system which activates most or all of the total number of processors when computational demands are high, i.e., a regular power state. Also, the DC power management system may idle (i.e., deactivate) a subset of the total number of processors when computational demands are low to minimize energy consumption, i.e., an idle power state. However, conventional DC power management systems tend to have large latencies if there is a need to wake up the processor systems while it is in the midst of entering a deep low power state. Hence, conventional DC power management systems incorporate DC power consumption inefficiencies and increase latency when a need for a DC power state change arises.